AI Driven Ultra Low Power VLSI Design Techniques for Wearable and IoT Devices

Chandrakala, B. (2025) AI Driven Ultra Low Power VLSI Design Techniques for Wearable and IoT Devices. World Journal of Advanced Engineering Technology and Sciences, 15 (3). pp. 2628-2636. ISSN 2582-8266

The rapid proliferation of wearable technologies and Internet of Things (IoT) devices has led to an urgent need for energy-efficient and ultra-low power (ULP) design solutions. These devices often operate in energy-constrained environments, relying on small batteries or energy harvesting sources. This research focuses on the development and optimization of ultra-low power VLSI design techniques to extend battery life and enhance the sustainability of such devices. Key strategies explored include sub-threshold and near-threshold operation, clock and power gating, dynamic voltage and frequency scaling (DVFS), energy-efficient memory architectures, and the integration of non-volatile elements for data retention during power-off states. Moreover, algorithm-level power optimization and AI-assisted design techniques are investigated to tailor computational loads to power budgets dynamically. Special emphasis is placed on hardware-software co-design approaches for wearable biomedical sensors and IoT nodes, ensuring real-time performance under strict power constraints. This work aims to contribute toward the realization of always-on, energy-autonomous systems essential for the next generation of smart, context-aware applications.