Threading models for network packet processing: Optimizing performance on low-end hardware

Babu, Thilak Raj Surendra (2025) Threading models for network packet processing: Optimizing performance on low-end hardware. World Journal of Advanced Engineering Technology and Sciences, 15 (2). pp. 2899-2907. ISSN 2582-8266

This article examines innovative threading architectures optimized for network packet processing on resource-constrained edge devices. As network functions increasingly migrate to the edge, traditional threading models designed for high-performance servers often create significant performance bottlenecks when deployed on limited hardware. The article analyzes the strengths and weaknesses of three primary threading models—run-to-completion, pipeline, and parallel approaches—and proposes hybrid solutions that adaptively combine their advantages. It introduces several key innovations: dynamic thread allocation that adjusts to changing traffic patterns, cache-aware thread scheduling that maximizes locality, lock-free synchronization mechanisms that reduce contention, and workload-aware pipeline adaptation that optimizes processing paths. Implementation considerations address thread creation overhead, queue management, memory access patterns, and performance diagnostics. Empirical testing demonstrates substantial improvements in throughput, latency, CPU utilization, and performance consistency across various workloads. These optimizations enable sophisticated network functions to be deployed on existing edge infrastructure without hardware upgrades, supporting the continued expansion of distributed network architectures in resource-constrained environments.